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elan microelect ronics corp. n o. 12, innovation 1 st rd., science-based industrial park hsin chu city, taiwan. tel: (03) 5639977 fax: (03) 5630118 em785830ad 8-bit micro-controller version 1.5
version history specification revision history version content efh5830ad 1.0 initial version 1.1 add 17.91mhz main clk 1.2 add efhp5830d, efhp5830ad, and efhp5830bd package 1.3 add the description about adc?s offset voltage 1.4 modify stack level from 16 to 12 modify program rom size from 4k to 16k rename ?efh5830d? to efh5830ad remove idle mode remove 17.9mhz main clk 1.5 rename from efh5830ad to em785830ad relative to em785830ad?s ro m-less, otp and mask: rom-less otp mask em78p5830d ice5830 em78p5830ad em785830ad difference betwee n em785830ad/em78p5830d/em78p5830ad some differences are betweenem785830ad, em78p5830d and em78p5830ad, these differences are list at next table: em78p5830d em78p5830ad em785830ad adis (code option bit9) un-effect un-effect must = 1 versel (code option bit10) un-effect must = 0 must = 0 pho (code option bit11) un-effect must = 0 must = 0 ms ( iocc page1 bit0) must = 1 un-effect un-effect stack number 16 16 12
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 1 12/14/2004 (v1.4) user application note (before using this chip, take a look at the followi ng description note, it incl udes important messages.) 1. there are some undefined bits in the registers. the values in these bits are unpredicted. these bits are not allowed to use. we use the symbol ?-? in the spec to recognize them. a fixed value must be write in some specific unused bits by software or some unpredicted wrong will occur these bits are as below: register register page bit default value initial setting value (by user software) effect r7 1 1 0 0 ram access will error ra 2 7 x 1 un-expect error rd 0 5~6 x 0 power consumption increase re 0 1~3 0 0 un-expect error ioc6 1 7 0 0 lcd display error ioc8 0 1~7 1 0 power consumption increase ioc8 1 1~7 0 0 power consumption increase ioca 1 3,6 x 0 power consumption increase iocb 0 0~7 1 0 power consumption increase iocc 0 4~7 1 0 power consumption increase iocc 1 0 x 1 ad function will error iocc 1 3~7 x 0 un-expect error ioce 0 0~3 0 0 un-expect error iocf 0 6~7 0 0 un-expect error 2. you will see some names for the register bits definitions. some name will be appear very frequently in the whole spec. the following descri bes the meaning for the register?s definitions such as bit type, bit name, bit number and so on. 76543 2 10 rab7 rab6 bab5 rab4 rab2 rab0 r/w-0 r/w-0 r-1 r/w-1 r r/w bit type bit name bit number read/write (default value=0) read/write (default value=1) read only (w/o default value) read/write (w/o default value) page0 ra register name and its page - rab1 (undefined) not allowed to use r-0 read only (default value=0) read only (default value=1) 3. always set iocc page1 bit 0 = 1 otherwise partial adc function cannot be used. 4. please do not switch mcu operation mode from norma l mode to sleep mode directly. before into sleep mode, please switch mcu to green mode. 5. while switching main clock (regar dless of high freq to low freq or on the other hand), adding 6 instructions delay (nop) is required. 6. offset voltage will effect adc ? s result, please refer to figure 20 to detail.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 2 12/14/2004 (v1.4) i. general description the em785830ad is an 8-bit risc type microprocessor with low power, high speed cmos technology. there are 16kx13 bits memory within it. this integrated single chip has an on_chip watchdog timer (wdt), program rom, data ram, lcd driver, programmable real time clock/counter, internal interrupt, power down mode, built-in three-wire spi, dual pwm(pulse width modulation), 6-channe l 10-bit a/d converter and tri-state i/o. ii. feature cpu operating voltage : 2.2v~5.5v at main clk less then 3.58mhz. main clk(hz) under 3.58m 7.16m 10.74m 14.3m operating voltage(min) 2.2 2.5 3 3.6 ?e 16k x 13 on chip program memory. ?e 0.5k x 8 on chip data ram ?e up to 31 bi-directional tri-state i/o ports ?e 12 level stack for subroutine nesting ?e 8-bit real time clock/counter (tcc) ?e two 8-bit counters : counter1 and counter2 ?e on-chip watchdog timer (wdt) ?e 99.9 h single instruction cycle commands ?e three operating modes (main clock can be programmed from 447.829k to 14.3mhz generated by internal pll) mode cpu status main clock 32.768khz clock status sleep mode turn off turn off turn off green mode turn on turn off turn on normal mode turn on turn on turn on input port interrupt function 12 interrupt source, 4 external, 8 internal dual clocks operation (internal pll main clock , external 32.768khz) spi serial peripheral interface (spi) : a kind of serial i/o interface interrupt flag available for the read buffer full or transmitter buffer empty. programmable baud rates of communication three-wire synchronous communication. (shared with io) pwm ?e dual pwm (pulse width modulation) with 10-bit resolution ?e programmable period (or baud rate) ?e programmable duty cycle adc operating : 2.5v ?? 5.5v 6-channel 10-bit successive approximation a/d converter internal (vdd) or external reference por power-on voltage detector reset lcd common driver pins : 4 segment driver pins : 13 1/3 bias 1/4 duty, 1/2 duty 16 level lcd contrast control by software package ?e em785830adq, em78p5830dq, EM78P5830ADQ ? 44 pin qfp
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 3 12/14/2004 (v1.4) iii. application communication or general product. iv. pin configuration em78p5830dq, EM78P5830ADQ em785830adq fig.1: 44-pin qfp assignment seg1 seg0 com3 com2 com1 com0 avdd pllc avss ad3/p62 ad6/p65 ad5/p64 ad4/p63 p67 adr/p66 ad1/p60 ad2/p61 xin xout /reset p80 p77 pc2/pwm2 pc1/pwm1 p70/int0 p73/int3 p74/sdi p75/sdo p76/sck p72/int2 p71/int1 pc0 pc3 p90/seg20 p91/seg19 p92/seg18 p93/seg17 p94/seg16 p95/seg15 p96/seg14 p97/seg13 p57/seg12 p56/seg11 p55/seg10 1 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 14 15 12 13 33 32 31 30 29 28 27 26 25 24 34 35 36 37 38 39 40 41 42 43 44
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 4 12/14/2004 (v1.4) v. functional block diagram timing control timer tcc counter1 counter2 wdt rom dataram control register lcd driver i/o port cpu spi pwm 10-bit a/d ram fig.2a block diagram xin pllc oscillator timing control r1(tcc) prescaler wdt timer general ram r4 interrupt control instruction decoder instruction register rom r3 r5 acc alu stack data & control bus xout r2 data ram control sleep and wakeup on i/o port spi pwm 10-bit a/d p60~p67 ioc6 r6 port6 p70~p77 ioc7 r7 port7 p90~p97 ioc9 r9 port9 pc0~pc3 iocc rc portc com0~com3 seg0~seg1 seg10~seg20 lcd ram driver p55~p57 ioc5 r5 port5 p80 ioc8 r8 port8 fig.2b block diagram
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 5 12/14/2004 (v1.4) vi. pin descriptions pin i/o description power avdd power power avss power ground clock xin i input pin for 32.768 khz oscillator xout o output pin for 32.768 khz oscillator pllc i phase loop lock capacitor, connect a capacitor 0.047u to 0.1u to the ground. lcd com0 ~ com3 o common driver pins of lcd drivers seg0 ~ seg1 seg10 ~ seg12 seg13 ~ seg20 o o (i/o : port5) o (i/o : port9) segment driver pins of lcd drivers seg10 to seg20 are shared with io port. 6 channel 10-bit a/d ad1 i (p60) adc input channel 1. shared with port60 ad2 i (p61) adc input channel 2. shared with port61 ad3 i (p62) adc input channel 3. shared with port62 ad4 i (p63) adc input channel 4. shared with port63 ad5 i (p64) adc input channel 1. shared with port64 ad6 i (p65) adc input channel 2. shared with port65 adr i (p66) adc external reference input. shared with port66 spi sck io (port76) master: output pin, slave: input pin. this pin shared with port76. sdo o (port75) output pin for serial data transferring. this pin shared with port75. sdi i (port74) input pin for receiving data. this pin shared with port74. pwm pwm1 o (pc1) pulse width modulation output channel 1. this pin is shared with pc1 pwm2 o (pc2) pulse width modulation output channel 2. the pin is shared with pc2 io p55~p57 i/o port5 can be input or output port each bit. port5(7:5) are shared with lcd segment signal. p60 ~p67 i/o port6 can be input or output port each bit. p70 ~ p77 i/o port7 can be input or output port each bit. port7(4~6) are shared with spi interface pins internal pull high function. port7(0~3) has interrupt function. p80 i/o p80 can be input or output port each bit. internal pull high. port80 have wake-up functions(set by re page0) p90 ~ p97 i/o port9 can be input or output port each bit. port90~93 are shared with adc input. port9 are shared with lcd segment signal. pc0 ~ pc3 i/o portc can be input or output port each bit. portc(1~2) are shared with pwm output pins int0 (port70) interru p t sources. once port70 has a fallin g ed g e or risin g ed g e si g nal
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 6 12/14/2004 (v1.4) (controlled by cont register), it will generate a interruption. int1 (port71) interrupt sources which has the same interrupt flag. any pin from port71 has a falling edge signal, it will generate a interruption. int2 (port72) interrupt sources which has the same interrupt flag. any pin from port72 has a falling edge signal, it will generate a interruption. int3 (port73) interrupt sources which has the same interrupt flag. any pin from port73 has a falling edge signal, it will generate a interruption. /reset i low reset
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 7 12/14/2004 (v1.4) vii. functional descriptions vii.1 operational registers register configuration r page registers addr r page0 r page1 r page2 r page3 00 indirect addressing 01 tcc 02 pc 03 page, status 04 ram bank, rsr 05 port5 i/o data, program rom page lcd ram address spi control pwm control 06 port6 i/o data lcd ram data buffer spi data buffer duty of pwm1 07 port7 i/o data data ram bank pwm1 control duty of pwm1 08 port8 i/o data data ram address period of pwm1 09 port9 i/o data data ram data buffer duty of pwm2 0a pll, main clock, wdte pwm2 control duty of pwm2 0b adc output data buffer period of pwm2 0c portc i/o data counter1 data 0d lcd control counter2 data 0e wake-up control, interrupt flag 0f interrupt flag 10 16 bytes : common registers 1f 20 bank0~bank3 : common registers 3f (32x8 for each bank) ioc page registers addr ioc page0 ioc page1 00 01 02 03 04 05 port5 i/o control, lcd bias control 06 port6 i/o control port6 switches 07 port7 i/o control port7 pull high 08 port8 i/o control port8 pull high 09 port9 i/o control port9 switches 0a
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 8 12/14/2004 (v1.4) 0b adc control 0c portc i/o control port5,8,b,c switch 0d clock source(cn1,cn2) prescaler(cn1,cn2) 0e interrupt mask 0f interrupt mask 10 : 1f 20 : 3f vii.2 operational regist er detail description r0 (indirect addressing register) r0 is not a physically implemented register. it is used as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). example: mov a, @0x20 ;store a address at r4 for indirect addressing mov 0x04, a mov a, @0xaa ;write data 0xaa to r20 at bank0 through r0 mov 0x00, a r1 (tcc) tcc data buffer. increased by 16.384khz or by the instruction cycle clock (controlled by cont register). written and read by the program as any other register. r2 (program counter) the structure is depicted in fig.3. generates 16k 13 on-chip program otp-rom addresses to the relative programming instruction codes. "jmp" instruction allows the direct loading of the low 10 program counter bits. "call" instruction loads the low 10 bits of the pc, pc+1, and then push into the stack. "ret'' ("retl k", "reti") instruction loads the program counter with th e contents at the top of stack. "mov r2, a" allows the loading of an address from the a register to the pc, and the ninth and tenth bits are cleared to "0''. "add r2,a" allows a relative a ddress be added to the current pc, and contents of the ninth and tenth bits are cleared to "0''. "tbl" allows a relative address added to the current pc, and contents of the ninth and tenth bits don't change. the most significant bit (a10~a11) will be loaded with th e contents of bit ps0~ps1 in the status register (r5 page0) upon the execution of a "jmp'', "call'', "add r2, a'', or "mov r2, a'' instruction. if an interrupt is triggered, program rom will jump to address 0x08 at page0. the cpu will store acc, r3 status and r5 page automatically, and they will be restored after instruction reti.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 9 12/14/2004 (v1.4) a9 a8 a7~a0 0 0 0 0 page0 00000~003ff 0 0 0 1 page1 00400~007ff 0 0 1 0 page2 00800~00bff stack1 stack2 stack5 stack4 stack3 stack6 stack8 stack7 stack9 stack10 stack11 call and interrupt ret retl reti acc,r3,r5(page) r5(page) store restore 1 1 1 1 page15 05400~057ff a13 a12 a11 a10 : : : stack12 fig.3 program counter organization r3 (status, page selection) (status flag, page selection bits) 7 6 5 4 3 2 1 0 rpage1 rpage0 iocpage t p z dc c r/w-0 r/w-0 r/w-0 r r r/w r/w r/w bit 0(c) : carry flag bit 1(dc) : auxiliary carry flag bit 2(z) : zero flag bit 3(p) : power down bit set to 1 during power on or by a "wdtc" co mmand and reset to 0 by a "slep" command. bit 4(t) : time-out bit set to 1 by the "slep" and "wdtc" command, or during power up and reset to 0 by wdt timeout. event t p remark wdt wake up from sleep mode 0 0 wdt time out (not sleep mode) 0 1 /reset wake up from sleep 1 0 power up 1 1 low pulse on /reset x x x : don't care bit 5(iocpage) : change ioc5 ~ ioce to another page 0/1 ? ioc page0 / ioc page1 please refer to vii.1 operational registers for detail ioc page register configuration. bit 6 ~ bit 7 (rpage0 ~ rpage1) : change r5 ~ re to another page (rpage1,rpage0) r page # selected (0,0) r page 0 (0,1) r page 1 (1,0) r page 2 (1,1) r page 3 please refer to vii.1 operational registers for detail r page register configuration.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 10 12/14/2004 (v1.4) r4 (ram selection for co mmon registers r20 ~ r3f)) (ram selection register) 7 6 5 4 3 2 1 0 rb1 rb0 rsr5 rsr4 rsr3 rsr2 rsr1 rsr0 r/w-0 r/w-0 r/w r/w r/w r/w r/w r/w bit 0 ~ bit 5 (rsr0 ~ rsr5) : indirect addressing for common registers r20 ~ r3f rsr bits are used to select up to 32 registers (r20 to r3f) in the indirect addressing mode. bit 6 ~ bit 7 (rb0 ~ rb1) : bank selection bits for common registers r20 ~ r3f these selection bits are used to determine which bank is activated among the 4 banks for 32 register (r20 to r3f).. please refer to vii.1 operational registers for details. r5 (port5 i/o data, program page selecti on, lcd address, spi control, pwm control) page0 (port5 i/o data register, program page register) 7 6 5 4 3 2 1 0 p57 p56 p55 0 ps3 ps2 ps1 ps0 r/w r/w r/w r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 3 (ps0 ~ ps3) : program page selection bits ps3 ps2 ps1 ps0 program me mory page (address) 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 : : : : : : : : : : 1 1 1 0 page 14 1 1 1 1 page 15 user can use page instruction to change page to maintain program page by user. bit 4 : (undefined) not allowed to use. these 2 bits mu st clear to 0 or some un predicted wrong will occur. bit 5 ~ bit 7 (p55 ~ p57) : 8-bit port5(5~7) i/o data register user can use ioc register to define input or output each bit. page1 (lcd address) 7 6 5 4 3 2 1 0 - - lcda3 lcda2 lcda1 lcda0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 3 (lcda0 ~ lcda3) : lcd address for lcd ram read or write the address of the lcd ram correspond to the common and segment signals as the table. com3 ~ com0 lcd address (lcda3 ~ lcda0) seg1, seg0 00h seg9 , seg2 un-exist seg11, seg10 05h seg13, seg12 06h seg15, seg14 07h seg17, seg16 08h seg19, seg18 09h seg20 0ah bit4~bit7 : (undefined) not allowed to use
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 11 12/14/2004 (v1.4) page2 (spi control) 7 6 5 4 3 2 1 0 rbf spie sro se sces sbr2 sbr1 sbr0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 spi module sck bit7 salve device spir register sdi spiw register spis reg sdo sdo sck sdi master device r5 page2 fig.4 single spi master / salve communication fig. 4 shows how spi to communicate with other device by spi module. if spi is a master controller, it sends clock through the sck pin. an 8-bit data is transmitted and received at the same time. if spi, however, is defined as a slave, its sck pin could be pr ogrammed as an input pin. data will continue to be shifted on a basis of both the clock rate and the selected edge. bit 0 ~ bit 2 (sbr0 ~ sbr2) : spi baud rate selection bits sbr2 sbr1 sbr0 mode baud rate 0 0 0 master fsco 0 0 1 master fsco/2 0 1 0 master fsco/4 0 1 1 master fsco/8 1 0 0 master fsco/16 1 0 1 master fsco/32 1 1 0 slave 1 1 1 master 16.384k fsco = cpu instruction clock for example : if pll is enabled and main clock is selected to 3.5826mhz, the instruction clock is 3.5826mhz/2 ? fsco=3.5862mhz/2 if pll is enabled and main clock is selected to 3.5826mhz, the instruction clock is 0.895mhz/2 ? fsco=0.895mhz/2 if pll is disabled, the instruction clock is 32.768khz/2 ? fsco=32.768khz/2. bit 3 (sces) : spi clock edge selection bit 1 ? data shifts out on falling edge, and shifts in on rising edge. data is hold during the high level. 0 ? data shifts out on rising edge, and shifts in on falling edge. data is hold during the low level. bit 4 (se) : spi shift enable bit 1 ? start to shift, and keep on 1 while th e current byte is still being transmitted. 0 ? reset as soon as the shifting is complete, and the next byte is ready to shift. this bit has to be reset in software. bit 5 (sro) : spi read overflow bit 1 ? a new data is received while the previous data is still be ing hold in the spib register. in this situation, the data in spis register will be destroyed. to avoid settin g this bit, users had better to read spib register even
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 12 12/14/2004 (v1.4) if the transmission is implemented only. 0 ? no overflow, this can only occur in slave mode. bit 6 (spie) : spi enable bit 1 ? enable spi mode 0 ? disable spi mode bit 7 (rbf) : spi read buffer full flag 1 ? receive is finished, spib is full. 0 ? receive is not finish yet, spib is empty. spis reg. read r5 page2 write r5 page2 spir reg. edge select shift right bit 0 bit 7 prescaler 4, 8, 16, 32, 64, 128 port74 port75 sck t sco 16.38khz sbr2~sbr0 3 clock select 2 noise filter spic reg. (r4 page1) sbr0 ~sbr2 rbf rbfi buffer full detector set to 1 spiwc sdo spie sdi mux spie 0 port76 mux sck spie 3 spiw reg. edge select mux sdi/p74 sdo/p75 sck/p76 fig.5 spi structure spic reg. : spi control register sdo/p75 : serial data out sdi/p74 : serial data in sck/p76 : serial clock rbf : set by buffer full detector, and reset in software. rbfi : interrupt flag. set by buffer full detector, and reset in software. buffer full detector : sets to 1, while an 8-bit shifting is complete. se : loads the data in spiw register, and begin to shift spie : spi control register spis reg. : shifting byte out and in. the msb will be shifted first. both the spis register a nd the spiw register are loaded at the same time. once data being written to, spis starts transmission / r eception. the received data will be moved to the spir register, as the shifting of the 8-bit data is comple te. the rbf (read buffer full ) flag and the rbfi(read buffer full interrupt) flag are set. spir reg. : read buffer. the buffer will be updated as the 8-b it shifting is complete. the data must be read before the next reception is finished. the rbf flag is cleared as the spir register read. spiw reg. : write buffer. the buffer will deny any write until the 8-bit shifting is complete. the se bit will be kept in 1 if the communication is still under going. this flag must be clear ed as the shifting is finished. users can determine if
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 13 12/14/2004 (v1.4) the next write attempt is available. sbr2 ~ sbr0: programming the cloc k frequency/rates and sources. clock select : selecting either the internal instruction cl ock or the external 16.338khz clock as the shifting clock. edge select : selecting the appropriate clock edges by programming the sces bit fig.6 spi timing page3 (pwmcon) 7 6 5 4 3 2 1 0 pwm2e pwm1e t2en t1en t2p1 t2p0 t1p1 t1p0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 1 ( t1p0 ~ t1p1 ): tmr1 clock prescale option bits. t1p1 t1p0 prescale 0 0 1:2(default) 0 1 1:8 1 0 1:32 1 1 1:64 bit 2 ~ bit 3 ( t2p0 ~ t2p1 ): tmr2 clock prescale option bits. t2p1 t2p0 prescale 0 0 1:2(default) 0 1 1:8 1 0 1:32 1 1 1:64 bit 4 (t1en): tmr1 enable bit 0 ? tmr1 is off (default value). 1 ? tmr1 is on. sdo rbf sck (sces=0) sck (sces=1) sdi shift data out shift data in clear by software bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 14 12/14/2004 (v1.4) bit 5 (t2en): tmr2 enable bit 0 ? tmr2 is off (default value). 1 ? tmr2 is on. bit 6 (pwm1e): pwm1 enable bit 0 ? pwm1 is off (default value), and its related pin carries out the pc1 function; 1 ? pwm1 is on, and its related pin will be set to output automatically. bit 7 (pwm2e): pwm2 enable bit 0 ? pwm2 is off (default value), and its related pin carries out the pc2 function. 1 ? pwm2 is on, and its related pin will be set to output automatically. r6 (port6 i/o data, lcd data, spi data buffer, pwm1 duty) page0 (port6 i/o data register) 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 8 (p60 ~ p67) : 8-bit port6(0~7) i/o data register user can use ioc register to define input or output each bit. page1 (lcd data) 7 6 5 4 3 2 1 0 lcdd7 lcdd6 lcdd 5 lcdd4 lcdd3 lcdd2 lcdd1 lcdd0 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (lcdd0 ~ lcdd7 ) : lcd data buffer for lcd ram read or write lcd data vs. com-seg lcdd7 ~ lcdd4 lcdd3 ~ lcdd0 com3 ~ com0 com3 ~ com0 lcd address (lcda3 ~ lcda0) seg1 seg0 00h seg11 seg10 05h seg13 seg12 06h seg15 seg14 07h seg17 seg16 08h seg19 seg18 09h x seg20 0ah page2 (spi data buffer) 7 6 5 4 3 2 1 0 spib7 spib6 spib5 spib4 spib3 spib2 spib1 spib0 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (spib0 ~ spib7) : spi data buffer if you write data to this register, the data will write to spiw register. if you read this data, it will read the data from spir register. please refer to figure7 page3 (dt1l: the least significant byte ( bit 7 ~ bit 0) of duty cycle of pwm1) 7 6 5 4 3 2 1 0 pwm1[7] pwm1[6] pwm1[5] pwm1[4] pwm1[3] pwm1[2] pwm1[1] pwm1[0] r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 r/w-0 a specified value keeps the output of pwm1 to stay at high until the value matches with tmr1.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 15 12/14/2004 (v1.4) r7 (port7 i/o data, data ram bank, pw m1 duty, adc output and resolution) page0 (port7 i/o data register) 7 6 5 4 3 2 1 0 p77 p76 p75 p74 p73 p72 p71 p70 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (p70 ~ p77) : 8-bit port7(0~7) i/o data register user can use ioc register to define input or output each bit. page1 (adc output data(8~9), ad resolution control, data ram bank selection bits) 7 6 5 4 3 2 1 0 - ad9 ad8 - adres 0 ram_b0 r r r/w-0 r/w-0 r/w-0 bit 0 (ram_b0) : data ram bank selection bits each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes ram size. data ram bank selection : (total ram = 0.5k) ram_b0 ram bank 0 bank0 1 bank1 bit 1 : unused. this bit must be 0. bit 2(adres) : resolution selection for adc 0 ? adc is 8-bit resolution when 8-bit resolution is selected, the most significant(msb) 8-bit data output of the internal 10-bit adc will be mapping to rb page1 so r7 page1 bit 4 ~5 will be of no use. 1 ? adc is 10-bit resolution when 10-bit resolution is selected, 10-bit data output of the internal 10-bit adc will be exactly mapping to rb page1 and r7 page1 bit 4 ~5. bit 3 : (undefined) not allowed to use bit 4 ~ bit 5(ad8 ~ ad9) : the most significant 2 bit of 10-bit adc conversion output data combine there two bits and rb page1 as complete 10-bit adc conversion output data. bit 6~bit7 : (undefined) not allowed to use page2 : (undefined) not allowed to use page3 (dt1h: the most significant byte ( bit 1 ~ bit 0 ) of duty cycle of pwm1) 7 6 5 4 3 2 1 0 - - - - - - pwm1[9] pwm1[8] r/w-0 r/w-0 bit 0 ~ bit 1 (pwm1[8] ~ pwm1[9]): the most significant byte of pwm1 duty cycle a specified value keeps the pwm1 output to stay at high until the value matches with tmr1. bit 2 ~ bit 7 : (undefined) not allowed to use. r8 (port8 i/o data, data ram address, pwm1 period) page0 (port8 i/o data register) 7 6 5 4 3 2 1 0 p80 r/w bit 0 (p80 ) : port80 i/o data register user can use ioc register to define this pin input or output each bit. bit1~bit7 : (undefined) not allowed to use
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 16 12/14/2004 (v1.4) page1 (data ram address register) 7 6 5 4 3 2 1 0 ram_a7 ram_a6 ram_a5 ram_ a4 ram_a3 ram_a2 ram_a1 ram_a0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 7 (ram_a0 ~ ram_a7) : data ram address the data ram bank?s selection is from r7 page1 bit0 (ram_b0). page2 : (undefined) not allowed to use page3 (prd1: period of pwm1) 7 6 5 4 3 2 1 0 prd1[7] prd1[6] prd1[5] prd1[4] prd1[3] prd1[2] prd1[1] prd1[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 the content of this register is a period (time base) of pwm1. the frequency of pwm1 is the reverse of the period. r9 (port9 i/o data, data ram data buffer, pwm2 duty) page0 (port9 i/o data register) 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (p90 ~ p97) : 8-bit port9(0~7) i/o data register user can use ioc register to define input or output each bit. page1 (data ram data register) 7 6 5 4 3 2 1 0 ram_d7 ram_d6 ram_d5 ram_ d4 ram_d3 ram_d2 ram_d1 ram_d0 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (ram_d0 ~ ram_d7) : data ram?s data the address for data ram is accessed from r8 page1. the data ram bank is selected by r7 page1 bit 0 (ram_b0). page2 (undefined) not allowed to use page3 (dt2l: the least significant byte ( bit 7 ~ bit 0 ) of duty cycle of pwm2) 7 6 5 4 3 2 1 0 pwm2[7] pwm2[6] pwm2[5] pwm2[4] pwm2[3] pwm2[2] pwm2[1] pwm2[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 a specified value keeps the output of pwm2 to stay at high until the value matches with tmr2. ra (pll, main clock selection, comparator flag, watchdog timer, pwm2 duty, lcd option) page0 (pll enable bit, main clock selection bits, co mparator control bits, watchdog timer enable bit) 7 6 5 4 3 2 1 0 0 pllen clk2 clk1 clk0 - - wdten r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 bit 0(wdten) : watch dog control bit 0/1 ? disable/enable
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 17 12/14/2004 (v1.4) user can use wdtc instruction to clear watch dog counter. the counter 's clock source is 32768/2 hz. if the prescaler assigns to tcc. watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. if the prescaler assigns to wdt, the time of time out will be more times depending on the ratio of prescaler. bit 1 ~ bit 2 : (undefined) not allowed to use bit 3 ~ bit 5 (clk0 ~ clk2) : main clock selection bits user can choose different frequency of main clock by clk1 and clk2. all the clock selection is list below. pllen clk2 clk1 clk0 sub clock main clock cpu clock 1 0 0 0 32.768khz 447.829khz 447.829khz (normal mode) 1 0 0 1 32.768khz 895.658khz 895.658khz (normal mode) 1 0 1 0 32.768khz 1.791mhz 1.791mhz (normal mode) 1 0 1 1 32.768khz 3.582mhz 3.582mhz (normal mode) 1 1 0 0 32.768khz 7.165mhz 7.165mhz (normal mode) 1 1 0 1 32.768khz 10.747mhz 10.747mhz (normal mode) 1 1 1 0 32.768khz 14.331mhz 14.331mhz (normal mode) 1 1 1 1 can?t allowed to used 0 don?t care don?t care don?t care 32.768khz don?t care 32.768khz (green mode) bit 6(pllen) : pll's power control bit which is cpu mode control register 0/1 ? disable pll/enable pll if enable pll, cpu will operate at normal mode (hig h frequency). otherwise, it will run at green mode (low frequency, 32768 hz). sub-clock 32.768khz switch 0 1 system clock pll circuit 447.8293khz ~14.3mhz enpll clk2 ~ clk0 fig.7 the relation between 32.768khz and pll bit 7: unused register. always keep this bit to 0 or some un-expect error will happen! the status after wake-up and the wake-up sources list as the table below. wakeup signal sleep mode ra(7,6)=(0,0) + slep tcc time out iocf bit0=1 no function counter1 time out iocf bit1=1 no function counter2 time out iocf bit2=2 no function wdt time out reset and jump to address 0 port7(0~3) reset and jum p to
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 18 12/14/2004 (v1.4) iocf bit3 or bit4 or bit5 or bit7=1 address 0 port70 's wakeup function is controlled by iocf bit 3. it's falling edge or rising edge trigger (controlled by cont register bit7). port7(1~3) 's wakeup functions are controlled by iocf bit (4,5,7). they are falling edge trigger. port80?s wakeup function is controlled by re page0 bit 0 . this is falling edge trigger. page1 (undefined, not allowed to use) page2 (undefined, not allowed to use) 7 6 5 4 3 2 1 0 1 x x x x x x x rw-0 - - - - - - - bit0~bit6 : (undefined) not allowed to use. bit 7 :unused. please set this bit to 1. page3 (dt2h: the most significant byte ( bit 1 ~ bit 0 ) of duty cycle of pwm2) 7 6 5 4 3 2 1 0 x x x x x x pwm2[9] pwm2[8] - - - - - - r/w-0 r/w-0 bit 0 ~ bit 1 (pwm2[8] ~ pwm2[9]): the most significant byte of pwm1 duty cycle a specified value keeps the pwm1 output to stay at high until the value matches with tmr1. bit 2 ~ bit 7 : (undefined) not allowed to use rb (adc output data buffer, pwm2 period) page0 (undefined, not allowed to use) page1 (adc output data register) 7 6 5 4 3 2 1 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r r r r r r r r bit 0 ~ bit 7 (ad0 ~ ad7) : these 8 bit is full adc data buffer when 8-bit resolution is selected(r7 page1 bit 2 adref = 0), or the least significant 8-bit data when 10 bit resolution(adref = 1) selected.. page2(undefined, not allowed to use) page3 (prd2: period of pwm2) 7 6 5 4 3 2 1 0 prd2[7] prd2[6] prd2[5] prd2[4] prd2[3] prd2[2] prd2[1] prd2[0] r/w-0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 the content of this register is a period (time base) of pwm2. the frequency of pwm2 is the reverse of the period. rc (portc i/o data, counter1 data, pwm1 duty latch) page0 (port9 i/o data register) 7 6 5 4 3 2 1 0 pc3 pc2 pc1 pc0 r/w r/w r/w r/w
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 19 12/14/2004 (v1.4) bit 0 ~ bit 3 (pc0 ~ pc3) : 4-bit portc(0~3) i/o data register user can use ioc register to define input or output each bit. bit4 ~ bit7 : undefined. not allowed to used . page1 (counter1 data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cn17 cn16 cn15 cn14 cn13 cn12 cn11 cn10 r/w-0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 7 (cn10 ~ cn17) : counter1's buffer that user can read and write. counter1 is a 8-bit up-counter with 8-bit prescaler that user can use rc page1 to preset and read the counter.(write ? preset) after a interruption , it will reload the preset value. example for writing : mov 0x0c, a ; write the data at accumulator to counter1 (preset) example for reading : mov a, 0x0c ; read the da ta at counter1 to accumulator page2 ( undefined, not allowed to use ) page3 ( undefined, not allowed to use ) rd (lcd control, counter2 data, pwm1,2 duty latch) page0 (lcd driver control bits) 7 6 5 4 3 2 1 0 - 0 0 1 - lcd_c1 lcd_c0 lcd_m r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 (lcd_m) : lcd operation method including duty and frame frequency bit 1 ~ bit 2 (lcd_c0 ~ lcd_c1) : lcd display control lcd_c1 lcd_c0 lcd_m lcd display control duty bias 0 0 0 change duty 1/4 1/3 1 disable(turn off lcd) 1/2 1/3 0 1 : blanking : : 1 1 : lcd display enable : : ps. to change the display duty must set the "lcd_c1 ,lcd_c0" to "00". the controller can drive lcd directly. the lcd block is made up of common driver, segment driver, display lcd ram, common output pins, segment output pins and lcd operating power supply. the basic structure contains a timing control. this timing control uses the basic fre quency 32.768khz to generate the proper timing for different duty and display access. rd page0 bit 0 ~ bit 2 are lcd control bits for lcd driver. these lcd control bits determine the duty, the number of common and the frame frequency. the lc d display (disable, enable, blanking) is controlled by bit 1 and bit 2. the driving duty is decided by bit 0. the display data is stored in lcd ram which address and data access controlled by registers r5 page1 and r6 page1. user can regulate the contrast of lcd display by ioc5 page0 bit 0 ~ bit 3 (bias0 ~ bias3). up to 16 levels contrast is convenient for better display. bit 3 , bit 7 : (undefined) not allowed to use bit4 ~ bit6 : these 3 bits are unused in mask/otp em785830, but they are us ed for ice5830. about the definition of these 3 bits, please refer to appendixii. in ice5830, please clear bit5 and bit6 to 0 and set bit4 to 1.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 20 12/14/2004 (v1.4) page1 (counter2 data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cn27 cn26 cn25 cn24 cn23 cn22 cn21 cn20 r/w-0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 7 (cn20 ~ cn27) : counter2's buffer that user can read and write. counter2 is a 8-bit up-counter with 8-bit prescaler that user can use rd page1 to preset and read the counter.(write ? preset) after a interruption, it will reload the preset value. example for writing : mov 0x0d, a ; write the data at accumulator to counter2 (preset) example for reading : mov a, 0x0d ; read the da ta at counter2 to accumulator page2 ( undefined, not allowed to use ) page3 ( undefined, not allowed to use ) re (interrupt flag, wake-up control, pwm2 duty latch) page0 (interrupt flag, wake-up control bits) 7 6 5 4 3 2 1 0 pwm2 rbf adi pwm1 0 0 0 /wup80 r/w r/w-0 r/w-0 r/w-0 r/w-0 bit 0 (/wup80) : port80 wake-up control, 0/1 ? disable/enable p80 pin wake-up function bit 1~bit 3 : undefined. these 3 bits must clear to 0 or unpred icted wrong will occur. bit 4 (pwm1) : pwm1 (pulse width modulation channel 1) interrupt flag set when a selected period is reached, reset by software. bit 5 (adi) : adc interrupt flag after a sampling bit 6 (rbf) : spi data transfer complete interrupt if spi's rbf signal has a rising edge signal (rbf set to "1" when transfer data completely), cpu will set this bit. bit 7 (pwm2) : pwm2 (pulse width modulation channel 2) interrupt flag set when a selected period is reached, reset by software. page1~page3( undefined, not allowed to use )
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 21 12/14/2004 (v1.4) rf (interrupt status) (interrupt status register) 7 6 5 4 3 2 1 0 int3 - int2 int1 int0 cnt2 cnt1 tcif r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 "1" means interrupt request, "0" means non-interrupt bit 0(tcif) : tcc timer overflow interrupt flag set when tcc timer overflows. bit 1(cnt1) : counter1 timer overflow interrupt flag set when counter1 timer overflows. bit 2(cnt2) : counter2 timer overflow interrupt flag set when counter2 timer overflows. bit 3(int0) : external int0 pin interrupt flag if port70 has a falling edge/rising edge (controlled by cont register) trigger signal, cpu will set this bit. bit 4(int1) : external int1 pin interrupt flag if port71 has a falling edge trigger signal, cpu will set this bit. bit 5(int2) : external int2 pin interrupt flag if port72 has a falling edge trigger signal, cpu will set this bit. bit 6 : (undefined) not allowed to use bit 7(int3) : external int3 pin interrupt flag if port73 has a falling edge trigger signal, cpu will set this bit. iocf is the interrupt mask register. user can read and clear. trigger edge as the table signal trigger tcc time out counter1 time out counter2 time out int0 falling rising edge int1 falling edge int2 falling edge int3 falling edge r10~r3f (general purpose register) r10~r3f (banks 0 ~ 3) : all are general purpose registers.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 22 12/14/2004 (v1.4) vii.3 special purpose registers a (accumulator) internal data transfer, or instruction operand holding it's not an addressable register. cont (control register) 7 6 5 4 3 2 1 0 p70eg int ts retb k pab psr2 psr1 psr0 bit 0 ~ bit 2 (psr0 ~ psr2) : tcc/wdt prescaler bits psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 bit 3(pab) : prescal er assignment bit 0/1 ? tcc/wdt bit 4(retbk) : return value backup control for interrupt routine 0 ? disable/enable when this bit is set to 1, the cpu will store acc,r3 st atus and r5 page automatically after an interrupt is triggered. and it will be restored after instruction reti. when this bit is set to 0, the user need to store acc, r3 and r5 page in user program. bit 5(ts) : tcc signal source 0 ? internal instruction cycle clock 1 ? 16.384khz bit 6 (int) : int enable flag 0 ? interrupt masked by disi or hardware interrupt 1 ? interrupt enabled by eni/reti instructions bit 7(p70eg) : interrupt edge type of p70 0 ? p70 's interruption source is a rising edge signal. 1 ? p70 's interruption source is a falling edge signal. cont register is readable (contr) and writable (contw). tcc and wdt : there is an 8-bit counter available as prescaler for the tcc or wdt. th e prescaler is available for the tcc only or wdt only at the same time. an 8 bit counter is available for tcc or wdt determined by the status of the bit 3 (pab) of the cont register. see the prescaler ratio in cont register. fig.8 depicts the circuit diagram of tcc/wdt.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 23 12/14/2004 (v1.4) fig.8 block diagram of tcc wdt ioc5 (port5 i/o control, lcd bias control) page0 (lcd bias control bits) 7 6 5 4 3 2 1 0 ioc57 ioc56 ioc55 - bias3 bias2 bias1 bias0 r/w-1 r/w-1 r/w-1 r/ w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 3 (bias0 ~ bias3) : lcd operation voltage selection. v1 = vdd * (1 - n/60) bias3 bias2 bias1 bias0 vop (=vdd-vlcd) example (vdd = 3v) 0 0 0 0 vdd * (1-0/60) 3v 0 0 0 1 vdd * (1-1/60) 2.95v 0 0 1 0 vdd * (1-2/60) 2.90v 0 0 1 1 vdd * (1-3/60) 2.85v 0 1 0 0 vdd * (1-4/60) 2.80v : : : : : : 1 1 0 1 vdd * (1-13/60) 2.35v 1 1 1 0 vdd * (1-14/60) 2.30v 1 1 1 1 vdd * (1-15/60) 2.25v bit 4 : (undefined) not allowed to use bit 5 ~ bit 7 (ioc55 ~ ioc57) : port5(5~7) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance 16.38khz
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 24 12/14/2004 (v1.4) vdd v1 v2 vlcd vdd v1 v2 vlcd vdd v1 v2 vlcd vdd v1 v2 vlcd frame com0 com1 com2 com3 vdd v1 v2 vlcd vdd v1 v2 vlcd seg seg dark light fig.10 lcd waveform for 1/3 bias, 1/4 duty
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 25 12/14/2004 (v1.4) vdd v1 v2 vlcd vdd v1 v2 vlcd frame com0 com1 vdd v1 v2 vlcd vdd v1 v2 vlcd seg seg dark light fig.11 lcd waveform for 1/3 bias, 1/2 duty ioc6 (port6 i/o control, p6* pins switch control) page0 (port6 i/o control register) 7 6 5 4 3 2 1 0 ioc67 ioc66 ioc65 ioc64 ioc63 ioc62 ioc61 ioc60 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 ~ bit 7 (ioc60 ~ ioc67) : port6(0~7) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance page1 (p6* pins switch control register) 7 6 5 4 3 2 1 0 - p66s p65s p64s p6 3s p62s p61s p60s r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 ?before using bit 0 ~ bit 6, please set ioce page1 b it0(ms) = 1 to enable these port switches function? bit 0(p60s) : select normal i/o port60 pin or channel 1 input ad1 pin of adc 0 ? p60 (i/o port60) pin is selected 1 ? ad1 (channel 1 input of adc) pin is selected bit 1(p61s) : select normal i/o port61 pin or channel 2 input ad2 pin of adc 0 ? p61 (i/o port61) pin is selected 1 ? ad2 (channel 2 input of adc) pin is selected bit 2(p62s) : select normal i/o port62 pin or channel 3 input ad3 pin of adc
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 26 12/14/2004 (v1.4) 0 ? p62 (i/o port62) pin is selected 1 ? ad3 (channel 3 input of adc) pin is selected bit 3(p63s) : select normal i/o port63 pin or channel 4 input ad4 pin of adc 0 ? p63 (i/o port63) pin is selected 1 ? ad4 (channel 4 input of adc) pin is selected bit 4(p64s) : select normal i/o port64 pin or channel 5 input ad5 pin of adc 0 ? p64 (i/o port64) pin is selected 1 ? ad5 (channel 5 input of adc) pin is selected bit 4(p65s) : select normal i/o port65 pin or channel 6 input ad6 pin of adc 0 ? p65 (i/o port65) pin is selected 1 ? ad6 (channel 6 input of adc) pin is selected bit 6(p66s) : select normal i/o port66 pin or external reference voltage input of adc 0 ? p66 (i/o port66) pin is selected and adc reference voltage come from internal vdd 1 ? vref (external reference voltage input of adc) pin is selected this bit can switch ad converter reference volta ge coming from internal or external voltage. if this bit set to internal, then the reference volta ge will be vdd and port66 is a normal i/o port. if it set to external reference voltage, then the voltage will connected to vref pin. bit 7 : (undefined) not allowed to use ioc7 (port7 i/o control, port7 pull high control) page0 (port7 i/o control register) 7 6 5 4 3 2 1 0 ioc77 ioc76 ioc75 ioc74 ioc73 ioc72 ioc71 ioc70 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 ~ bit 7 (ioc70 ~ ioc77) : port7(0~7) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance page1 (port7 pull high control register) 7 6 5 4 3 2 1 0 ph77 ph76 ph75 ph74 ph73 ph72 ph71 ph70 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 7 (ph70 ~ ph77) : port7 bit0~bit7 pull high control register 0 ? disable pull high function. 1 ? enable pull high function ioc8 (port8 i/o control, port8 pull high control) page0 (port8 i/o control register) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ioc80 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 (ioc80) : port80 i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance bit 1~bit 7 : undefined, not allow to use. ** this 7 bits must clear to 0 or mcu power consumption will increase. the default value in these 7 bits are ?1?. please clear them to ?0? when init mcu.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 27 12/14/2004 (v1.4) page1 (port8 pull high control register) 7 6 5 4 3 2 1 0 ph80 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 (ph80) : port8 bit0 pull high control register 0 ? disable pull high function. 1 ? enable pull high function bit 1~bit 7 : undefined, not allow to use. ** this 7 bits must clear to 0 or mcu power consumption will increase. ioc9 (port9 i/o control, port9 switches) page0 (port9 i/o control register) 7 6 5 4 3 2 1 0 ioc97 ioc96 ioc95 ioc94 ioc93 ioc92 ioc91 ioc90 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 ~ bit 7 (ioc90 ~ ioc97) : port9(0~7) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance page1 (port9 switches) 7 6 5 4 3 2 1 0 p97s p96s p95s p94s p93s p92s p91s p90s r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0(p90s) : switch i/o port90 or lcd segment signal 0 ? (p90 pin is selected) : normal port90 1 ? (seg20 pin) : segment output bit 1(p91s) : switch i/o port91 or lcd segment signal 0 ? (p91 pin is selected) : normal port91 1 ? (seg19 pin) : segment output bit 2(p92s) : switch i/o port92 or lcd segment signal 0 ? (p92 pin is selected) : normal port92 1 ? (seg18 pin) : segment output bit 3(p93s) : switch i/o port93 or lcd segment signal 0 ? (p93 pin is selected) : normal port93 1 ? (seg17 pin) : segment output bit 4(p94s) : switch i/o port94 or lcd segment signal 0 ? (p94 pin is selected) : normal port94 1 ? (seg16 pin) : segment output bit 5(p95s) : switch i/o port95 or lcd segment signal 0 ? (p95 pin is selected) : normal port95 1 ? (seg15 pin) : segment output bit 6(p96s) : switch i/o port96 or lcd segment signal 0 ? (p96 pin is selected) : normal port96 1 ? (seg14 pin) : segment output bit 7(p97s) : switch i/o port97 or lcd segment signal 0 ? (p97 pin is selected) : normal port97 1 ? (seg13 pin) : segment output
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 28 12/14/2004 (v1.4) ioca (reserved) page0(undefined) not allowed to use page1(undefined) not allowed to use 7 6 5 4 3 2 1 0 - 0 - - 0 - r/w r/w bit0~bit1 : undefined. bit3 , bit6 (unused) : these 2 bits must clea r to 0 or mcu power consumption will increase. iocb (adc control) page0 (unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ** this page must clear to 0 or mcu power consumption will increase. the default value in these 8 bits are ?1?. please clear them to ?0? when init mcu. page1 (adc control bits) 7 6 5 4 3 2 1 0 in2 in1 in0 adclk1 adclk0 adpwr - adst r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0(adst) : ad converter start to sample by setting to ?1?, the ad will start to sample data. th is bit will be cleared by hardware automatically after a sampling. bit 1 : (undefined) not allowed to use bit 2(adpwr) : ad converter power control, 1/0 ? enable/disable bit 3 ~ bit 4 (adclk0 ~ adclk1) : ad circuit ?s sampling clock source. for pll clock = 895.658khz ~ 14.3mhz (clk2~clk0 = 001 ~ 111) adclk1 adclk0 sampling rate operation voltage 0 0 74.6k >=3.5v 0 1 37.4k >=3.0v 1 0 18.7k >=2.5v 1 1 9.3k >=2.5v for pll clock = 447.829khz (clk2~clk0 = 000) adclk1 adclk0 sampling rate operation voltage 0 0 37.4k >=3.0v 0 1 18.7k >=3.0v 1 0 9.3k >=2.5v 1 1 4.7k >=2.5v this is a cmos multi-channel 10-bit su ccessive approximation a/d converter. features 74.6khz maximum conversion speed at 5v. adjusted full scale input external reference voltage input or internal(vdd) reference voltage 8 analog inputs multiplexed into one a/d converter power down mode for power saving a/d conversion complete interrupt interrupt register, a/d control and status register, and a/d data register
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 29 12/14/2004 (v1.4) fig.12 adc sampling clock control logic fpll mx fs fadcon = fadc / 12 nx = 1 nx = 2 nx = 4 nx = 8 14.331mhz 16 895.658khz 74.638khz 37.391khz 18.659khz 9.329khz 10.747mhz 12 895.658khz 74.638khz 37.391khz 18.659khz 9.329khz 7.165mhz 8 895.658khz 74.638khz 37.391khz 18.659khz 9.329khz 3.582mhz 4 895.658khz 74.638khz 37.391khz 18.659khz 9.329khz 1.791mhz 2 895.658khz 74.638khz 37.391khz 18.659khz 9.329khz 895.658khz 1 895.658khz 74.638khz 37.391khz 18.659khz 9.329khz 447.829khz 1 447.829khz 37.391khz 18.659khz 9.329khz 4.665khz bit 5 ~ bit 7(in0~ in2) : input ch annel selection of ad converter these two bits can choose one of three ad input. in2 in1 in0 input pin 0 0 0 ad1 p60 0 0 1 ad2 p61 0 1 0 ad3 p62 0 1 1 ad4 p63 1 0 0 ad5 p64 1 0 1 ad6 p65 iocc (portc i/o control, adc control) page0 (portc i/o control register) 7 6 5 4 3 2 1 0 0 0 0 0 iocc3 iocc2 iocc1 iocc0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 ~ bit 3 (iocc0 ~ iocc3) : portc( 0~3) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance bit 4~bit 7 : undefined, not allow to use. ** these 4 bits must clear to 0 or mcu power consumption will increase. the default value in these 4 bits are ?1?. please clear them to ?0? when init mcu. page1 (port switch) 7 6 5 4 3 2 1 0 0 0 0 0 0 p5sh - ms r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0(ms) : p6* switch mode selection 0 ? (default unknown) 1 ? adc input mode selection (always set this bit to ?1? otherwise partial adc function cannot be used) programmable divider 1/mx divider nx 10-bit adc adclk1~adclk0 fs adc output pll enpll clk2 ~ clk0 fpll fadc
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 30 12/14/2004 (v1.4) bit 1: (undefined) not allowed to use bit 2(p5sh) : switch i/o port5 high nibble(5~7) or lcd segment signal 0 ? (p55 ~ p57 pins are selected) : normal port5 high nibble(5~7) 1 ? (seg10 ~ seg12 pins are selected) : segment output bit 3 ~ bit 7: (undefined) not allowed to use. please keep these bits to 0. iocd (clock source, prescaler of cn1 and cn2) page0: (undefined) not allowed to use page1 (clock source and prescaler for counter1 and counter2) 7 6 5 4 3 2 1 0 cnt2s c2_psc2 c2_psc1 c2_psc0 c nt1s c1_psc2 c1_psc1 c1_psc0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 2 (c1_psc0 ~ c1_psc2) : counter1 prescaler ratio c1_psc2 c1_psc1 c1_psc0 counter1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3(cnt1s) : counter1 clock source 0/1 ? 16.384khz/system clock bit 4 ~ bit 6 (c2_psc0 ~ c2_psc2) : counter2 prescaler ratio c2_psc2 c2_psc1 c2_psc0 counter2 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 7(cnt2s) : counter2 clock source 0/1 ? 16.384khz/system clock ioce (interrupt mask) page0 (interrupt mask) 7 6 5 4 3 2 1 0 pwm2 rbf adi pwm1 - - - - r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 3 : unused bit 4(pwm1) : pwm1 one period reach interrupt mask. bit 5 (adi) : adc conversion complete interrupt mask 0/1 ? disable/enable interrupt there are four registers for a/d converter. use one bit of interrupt control register (ioce page0 bit5) for a/d conversion complete interrupt. the status and control register of a/d (iocb page1 and re page0 bit5) responses the a/d conversion status or takes control on a/d. the a/d data register (rb page1) stores a/d conversion result. adi bit in ioce page0 register is end of a/d co nversion complete interrupt enable/disable. it
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 31 12/14/2004 (v1.4) enables/disables adi flag in re register when a/d conv ersion is complete. adi flag indicates the end of an a/d conversion. the a/d converter sets the interrupt fl ag, adi in re page0 register when a conversion is complete. the interrupt can be disabled by setting adi bit in ioce page0 bit5 to ?0?. the a/d converter has 6 analog input channels ad1~ad8 multiplexed into one sample and hold to a/d module. reference voltage can be driven from vref pin or internal power. the a/d converter itself is of an 8-bit successive approximation type and produces an 8-bit result in the rb page1 data register. a conversion is initiated by setting a control bit ad st in iocb page1 bit0. prior to conversion, the appropriate channel must be selected by setting in0~in1 bits in re register and allowed for enough time to sample data. every conversion data of a/d need 12-clock cycle time. the minimum conversion time required is 13 us (73k sample ra te). adst bit in iocb page1 bit0 mu st be set to begin a conversion. it will be automatically reset in hardware when conversion is complete. at the end of conversion, the start bit is cleared and the a/d interrupt is activated if adi in ioce page0 b it5 = 1. adi will be set when conversion is complete. it can be reset in software. if adi = 0 in ioce page0 bit5, when a/d start conversion by setting adst(iocb page1 bit0) = 1 then a/d will continue conversion without stop and hardware won?t reset adst bit. in this condition, adi is deactived. after adi in ioce page0 bit5 is set, adi in re page0 bit5 will activate again. to minimum operating current , all biasing circuits in the a/d module that consume dc current are power down when adpwr bit in iocb page1 bit2 register is a ?0?. when adpwr bit is a ?1?, a/d converter module is operating. user has to set port60~port65 as ad converter input pin or bi-direction io port fig.14 a/d converter timing bit 6 (rbf) : spi?s rbf interrupt mask 0/1 ? disable/enable interrupt bit 7 (pwm2) : pwm2 interrupt enable bit 0/1 ? disable/enable interrupt iocf (interrupt mask) (interrupt mask register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int3 - int2 int1 int0 cnt2 cnt1 tcif r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ 5,7 : interrupt enable bit 0 ? disable interrupt 1 ? enable interrupt bit 6 : (remain these values to ?0?othwise it will generate unpredicted interrupts) start sample adi(ioce page0 bit5 ) =1 adi(re page0 bit 5) data clear by software 1 2 3 4 5 6 7 8 9 10 11 12
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 32 12/14/2004 (v1.4) the status after interrupt and the interrupt sources list as the table below. interrupt signal green mode normal mode ra(7,6)=(x,0) no slep ra(7,6)=(x,1) no slep tcc time out iocf bit0=1 and "eni" interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) counter1 time out iocf bit1=1 and "eni" interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) counter2 time out iocf bit2=2 and "eni" interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) port7(0~3) iocf bit3 or bit4 or bit5 or bit7=1 and "eni" interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) rbf ioce bit6 = 1 and ?eni interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) adi ioce bit5 = 1 and ?eni no function interrupt (jump to address 8 at page0) pwm1 ioce bit4 = 1 and ?eni interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) pwm2 ioce bit7 = 1 and ?eni interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) port70 's interrupt function is controlled by iocf bit 3. it's falling edge or rising edge trigger (controlled by cont register bit7). port7(1~3) 's wakeup functions are controlled by iocf bit (4,5,7). they are falling edge trigger. adi interrupt source function is controlled by re page 0 bit 5. it is rising edge trigger after adc sample complete. it only happens when master and 16.386khz mode is selected.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 33 12/14/2004 (v1.4) vii.4 i/o port the i/o registers are bi-directional tri-state i/o ports. the i/o ports can be defined as "input" or "output" pins by the i/o control registers under program control. the i/o data registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig.15. fig.15 the circuit of i/o port and i/o control register vii.5 reset the reset can be caused by (1) wdt timeout. (if enabled and in green or normal mode) (2) /reset pin pull low once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? when power on, the upper 3 bits of r3 and the upper 2 bits of r4 are cleared. ? the watchdog timer and pres caler counter are cleared. ? the watchdog timer is disabled. ? the cont register is set to all "1" ? the other register (bit 7 ~ bit 0) default values are as follows. m u x 0 1 pdrd pdwr clk c l p r d q q clk c l p r d q q pcwr iod pcrd port
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 34 12/14/2004 (v1.4) operation registers : address r register page0 r register page1 r register page2 r register page3 ioc register page0 ioc register page1 0x4 00xxxxxx 0x5 xxxx0000 xxxx0000 00000000 00000000 111x0000 0x6 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 11111111 00000000 0x7 xxxxxxxx xxxx0000 xxxxxx00 11111111 00000000 0x8 xxxxxxxx 00000000 00000000 11111111 00000000 0x9 xxxxxxxx xxxxxxxx 00000000 11111111 00000000 0xa 00011xx0 11111111 0x000000 xxxxxx00 xxxxxxxx x0xx0xx 0xb xxxxxxxx xxxxxxxx xxxxxxxx 00000000 11111111 000000x0 0xc xxxxxxxx 00000000 xxxxxxxx 11111111 00000000 0xd xxxxx000 00000000 xxxxxxxx xxxxxxxx 00000000 0xe 00000000 xxxxxxxx 0000xxxx xxxxxxxx 0xf 00000000 00000000 vii.6 wake-up the controller provided sleep mode for power saving : (1) sleep mode, ra(7) = 0 + "slep" instruction the controller will turn off all the cp u and crystal. other circuit with power control like key tone control or pll control (which has enable register), user has to turn it off by software. wake-up from sleep mode (1) wdt time out (2) external interrupt (3) /reset pull low all these cases will reset controller , and run the program at address zero. the status ju st like the power on reset.. vii.7 interrupt rf is the interrupt status register which records the inte rrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008h. once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the rf register. the interrupt flag bit must be clear ed in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 35 12/14/2004 (v1.4) vii.8 instruction set instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general regist er. that is, the same instruction can operates on i/o register. the symbol "r" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. "b'' represents a b it field designator which selects the number of the bit, located in the register "r'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. instruction binary hex mnemonic operation status affected instruction cycle 0 0000 0000 0000 0000 nop no operation none 1 0 0000 0000 0001 0001 daa decimal adjust a c 1 0 0000 0000 0010 0002 contw a cont none 1 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t,p 1 0 0000 0000 0100 0004 wdtc 0 wdt t,p 1 0 0000 0000 rrrr 000r iow r a iocr none 1 0 0000 0001 0000 0010 eni enable interrupt none 1 0 0000 0001 0001 0011 disi disable interrupt none 1 0 0000 0001 0010 0012 ret [top of stack] pc none 2 0 0000 0001 0011 0013 reti [top of stack] pc enable interrupt none 2 0 0000 0001 0100 0014 contr cont a none 1 0 0000 0001 rrrr 001r ior r iocr a none 1 0 0000 0010 0000 0020 tbl r2+a r2 bits 9,10 do not clear z,c,dc 2 0 0000 01rr rrrr 00rr mov r,a a r none 1 0 0000 1000 0000 0080 clra 0 a z 1 0 0000 11rr rrrr 00rr clr r 0 r z 1 0 0001 00rr rrrr 01rr sub a,r r-a a z,c,dc 1 0 0001 01rr rrrr 01rr sub r,a r-a r z,c,dc 1 0 0001 10rr rrrr 01rr deca r r-1 a z 1 0 0001 11rr rrrr 01rr dec r r-1 r z 1 0 0010 00rr rrrr 02rr or a,r a v r a z 1 0 0010 01rr rrrr 02rr or r,a a v r r z 1 0 0010 10rr rrrr 02rr and a,r a & r a z 1 0 0010 11rr rrrr 02rr and r,a a & r r z 1 0 0011 00rr rrrr 03rr xor a,r a r a z 1 0 0011 01rr rrrr 03rr xor r,a a r r z 1 0 0011 10rr rrrr 03rr add a,r a + r a z,c,dc 1 0 0011 11rr rrrr 03rr add r,a a + r r z,c,dc 1 0 0100 00rr rrrr 04rr mov a,r r a z 1 0 0100 01rr rrrr 04rr mov r,r r r z 1 0 0100 10rr rrrr 04rr coma r /r a z 1
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 36 12/14/2004 (v1.4) 0 0100 11rr rrrr 04rr com r /r r z 1 0 0101 00rr rrrr 05rr inca r r+1 a z 1 0 0101 01rr rrrr 05rr inc r r+1 r z 1 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 2 if skip 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 2 if skip 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1) r(0) c, c a(7) c 1 0 0110 01rr rrrr 06rr rrc r r(n) r(n-1) r(0) c, c r(7) c 1 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1) r(7) c, c a(0) c 1 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1) r(7) c, c r(0) c 1 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7) r(4-7) a(0-3) none 1 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 1 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none 2 if skip 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 2 if skip 0 100b bbrr rrrr 0xxx bc r,b 0 r(b) none 1 0 101b bbrr rrrr 0xxx bs r,b 1 r(b) none 1 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 2 if skip 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 2 if skip 1 00kk kkkk kkkk 1kkk call k pc+1 [sp] (page, k) pc none 2 1 01kk kkkk kkkk 1kkk jmp k (page, k) pc none 2 1 1000 kkkk kkkk 18kk mov a,k k a none 1 1 1001 kkkk kkkk 19kk or a,k a k a z 1 1 1010 kkkk kkkk 1akk and a,k a & k a z 1 1 1011 kkkk kkkk 1bkk xor a,k a k a z 1 1 1100 kkkk kkkk 1ckk retl k k a, [top of stack] pc none 2 1 1101 kkkk kkkk 1dkk sub a,k k-a a z,c,dc 1 1 1110 0000 0001 1e01 int pc+1 [sp] 001h pc none 1 1 1110 100k kkkk 1e8k page k k->r5(4:0) none 1 1 1111 kkkk kkkk 1fkk add a,k k+a a z,c,dc 1 **1 instruction cycle = 2 main clk
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 37 12/14/2004 (v1.4) vii.9 code option code option register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pho versel adis mer bit 3(mer) : memory error recover function 0 ? disable memory error recover function 1 ? enable memory error recovery function if user enable memory error recovery function, mcu will improve effect from environment noise. bit 9(adis) : please set this bit to 1. bit 10 (versel): please clear this bit to 0. bit 11 (pho): please clear this bit to 0. vii.10 dual sets of pwm (pulse width modulation) (1) overview in pwm mode, both pwm1 and pwm2 pins produce up to a 10-bit resolution pwm output (see. fig.16 for the functional block diagram). a pwm output has a period and a duty cycle, and it keeps the output in high. the baud rate of the pwm is the inverse of the period. fig.17 depicts the relationships between a period and a duty cycle. data bus data bus prd1 comparator comparator tmr1h + tmr1l s rq mux duty cycle match period match p wm 1 t1p0 t1p1 t1en ioc6 prd2 comparator comparator s rq mux duty cycle match period match pwm2 t2p0 t2p1 t2en ioc6 to pwm1if to pwm2if reset reset latch latch 1:2 1:8 1:32 fosc 1:64 1:2 1:8 1:32 fosc 1:64 tmr2h + tmr2l dt2h + dt2l dt2h + dt2l dl2h + dl2l dl2h + dl2l fig.16 the functional block diagram of the dual pwms
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 38 12/14/2004 (v1.4) period duty cycle dt1 = tmr1 prd1 = tmr1 fig.17 the output timing of the pwm (2) increment timer counter ( tmrx: tmr1h/twr1l or tmr2h/twr2l ) tmrx are ten-bit clock counters with programmable pr escalers. they are designed for the pwm module as baud rate clock generators. tmrx can be read , written, and cleared at any reset conditions. if employed, they can be turned down for power saving by setting t1en bit [pwmcon<4>] or t2en bit [pwmcon<5>] to 0. (3) pwm period ( prdx : prd1 or prd2 ) the pwm period is defined by writing to the prdx register. when tmrx is equal to prdx, the following events occur on the next increment cycle: ? tmrx is cleared. ? the pwmx pin is set to 1. ? the pwm duty cycle is latched from dt1/dt2 to dtl1/dtl2. < note > the pwm output will not be set, if the duty cycle is 0; ? the pwmxif pin is set to 1. the following formula describes how to calculate the pwm period: period = (prdx + 1) * 4 * (1/fosc) * (tmrx prescale value ) where fosc is system clock (4) pwm duty cycle ( dtx: dt1h/ dt1l and dt2h/ dt2l; dtl: dl1h /dl1l and dl2h/dl2l ) the pwm duty cycle is defined by writing to the dt x register, and is latched from dtx to dlx while tmrx is cleared. when dlx is eq ual to tmrx, the pwmx pin is cleared. dtx can be loaded at any time. however, it cannot be latched into dtl until the current value of dlx is equal to tmrx. the following formula describes how to calculate the pwm duty cycle: duty cycle = (dtx) * (1/fosc) * (tmrx prescale value ) (5) comparator x to change the output status while the match occurs, the tmrxif flag will be set at the same time. (6) pwm programming procedures/steps load prdx with the pwm period. (1) load dtx with the pwm duty cycle. (2) enable interrupt function by writing iocf pafe0, if required. (3) set pwmx pin to be output by writing a desired value to iocc page0. (4) load a desired value to r5 page3 with tmrx prescaler value and enable both pwmx and tmrx. (7) timer timer1 (tmr1) and timer2 (tmr2) (tmrx) are 10-bit clock counters with programmable prescalers, respectively. they are designed for the pwm module as baud rate clock generators. tmrx can be read, written, and cleared at any reset conditions. the figure in the next page shows tmrx block diag ram. each signal and block are described as follows:
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 39 12/14/2004 (v1.4) data bus data bus prd1 comparator tmr1x mux period match t1p0 t1p1 t1en prd2 comparator tmr2x mux period match t2p0 t2p1 t2en to pwm1if to pwm2if reset reset 1:2 1:8 1:32 f osc 1:64 1:2 1:8 1:32 fosc 1:64 *tmr1x = tmr1h + tmr1l; *tmr2x = tmr2h +tmr2l fig.18 tmrx block diagram ? fosc: input clock. ? prescaler ( t1p0 and t1p1/t2p1 and t2p0 ): options of 1:2, 1:8, 1:32, and 1:64 are defined by tmrx. it is cleared when any type of reset occurs. ? tmr1x and tmr2x (tmr1h/twr1l and tmr2h/tmr2 l ):timer x register; tmrx is increased until it matches with prdx, and then is reset to 0. tmrx cannot be read. ? prdx ( prd1 and prd2 ): pwm period register. ? comparatorx ( comparator 1 and comparator 2 ): to reset tmrx while a match occurs and the tmrxif flag is set at the same time. when defining tmrx, refer to the related registers of its operation as shown in prescale register. it must be noted that the pwmx bits must be disabled if their related tmrxs are employed. that is, bit 7 and bit 6 of the pwmcon register must be set to ?0?. related control registers(r5 page3) of tmr1 and tmr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm2e pwm1e t2en t1en t2p1 t2p0 t1p1 t1p0 timer programming procedures/steps (1) load prdx with the timer period. (2) enable interrupt function by writing iocf page0, if required (3) load a desired value to pwmcon with the tmrx prescaler value and enable both tmrx and disable pwmx.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 40 12/14/2004 (v1.4) viii. absolute operation maximum ratings rating symbol value unit dc supply voltage vdd -0.3 to 6 v input voltage vin -0.5 to vdd +0.5 v operating temperature range ta 0 to 70 j ix. dc electrical characteristic (ta = 25 c, avdd=vdd=5v 5%, vss=0v) parameter symbol condition min typ max unit input leakage current for input pins iil1 vin = vdd, vss 1 a input leakage current for bi- directional pins iil2 vin = vdd, vss 1 a input high voltage vih 2.5 v input low voltage vil 0.8 v input high threshold voltage viht /reset, tcc 2.0 v input low threshold voltage vilt /reset, tcc 0.8 v clock input high voltage vihx osci 3.5 v clock input low voltage vilx osci 1.5 v output high voltage for port5,b,c voh1 ioh = -6ma 2.4 v output high voltage for port6,7,8 voh2 ioh = -10ma 2.4 v output high voltage for port9 voh3 ioh = -20ma 2.4 v output low voltage for port5,b,c vol1 ioh = 6ma 0.4 v output low voltage for port6,7,8 vol2 ioh = 10ma 0.4 v output low voltage for port9 vol3 ioh = 20ma 0.4 v lcd drive reference voltage vlcd vdd=5v, contrast adjust 4 ~ 5 v pull-high current iph pull-high active input pin at vss -10 -15 a power down current (sleep mode) isb1 all input and i/o pin at vdd, output pin floating, wdt disabled 4 8 a low clock current (green mode) isb2 clk=32.768khz, all analog circuits disabled, all input and i/o pin at vdd, output pin floating, wdt disabled, lcd enabled 35 50 a operating supply current (normal mode) icc1 /reset=high, clk=3.582mhz, all analog circuits disabled, output pin floating 1 2 ma
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 41 12/14/2004 (v1.4) xi. ac electrical characteristic cpu instruction timing (ta = 25 c, avdd=vdd=5v, vss=0v) parameter symbol condition min typ max unit input clk duty cycle dclk 45 50 55 % instruction cycle time tins 32.768khz 3.582mhz 60 550 us ns device delay hold time tdrh 16 ms tcc input period ttcc note 1 (tins+20)/n ns watchdog timer period twdt ta = 25 c 16 ms note 1: n= selected prescaler ratio. adc characteristic (vdd = 5v, ta = +25 c, for internal reference voltage) parameter symbol condition min typ max unit upper bound offset voltage vofh 44 52.8 mv lower bound offset voltage vofl 32 38.4 mv *these parameters are characterized bu t not tested. * about adc characteristic, please refer to next page. timing characteristic (avdd=vdd=5v,ta=+25 c) description symbol min typ max unit oscillator timing characteristic osc start up 32.768khz toscs 400 1500 ms 3.579mhz pll 5 10 us spi timing characteristic (cpu clock 3.58mhz and fsco = 3.58mhz /2) /ss set-up time tcss 560 ns /ss hold time tcsh 250 sclk high time thi 250 ns sclk low time tlo 250 ns sclk rising time tr 15 30 ns sclk falling time tf 15 30 ns sdi set-up time to the reading edge of sclk tisu 25 ns sdi hold time to the reading edge of sclk tihd 25 ns sdo disable time tdis 560 ns timing characteristic of reset the minimum width of reset low pulse trst 3 us the delay between reset and program start tdrs 18 ms
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 42 12/14/2004 (v1.4) vdd osc power on reset /reset tdrs toscs program active tdrs trst the relative between osc stable time and power on reset em785830ad operation voltage(x axis ? min vdd ; y axis ? main clk): 5.5 4 3.6 mhz v 14.33 10.74 3.0 2.5 7.16 3.58 1.79 2.2 fig.19 the relative between operating voltage and main clk
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 43 12/14/2004 (v1.4) em785830ad?s 10 bit adc characteristic em785830ad build in 10 bit resolution, multi channel adc function. in ideal, if adc?s reference voltage is 5v, the adc?s lsb will be 5v/1024. but in practical, for some ph ysics or circuit?s character, some un-ideal will effect the converter result. as the next figure, offset voltage will reduce ad?s converter range. if ad?s input voltage less than vofl, adc will output 0; in opposition, if input voltage is larger than (vdd-vofh), adc will outp ut 1023. that is to say the physics ad converter range will replace by (vdd-vofh+lsb- vofl+lsb). if we defined that vrb = vofl ? lsb and vrt = vdd-vofh+lsb, the physics lsb is: lsb = (vrt - vrb) / 1024 = (vdd ? (vofh+vofl) ) / 1022 for real operating, please think about the effect of ad?s offset voltage. if converter the range of (vrt - vrb), the ad converter?s opposite result will be prcised. 0v vdd min. input for adc output = 1023 10-bit adc (for 10-bit adc, internally it takes this range to average 1024 steps) vofl vofh vrb vrt min. input for adc output = 1 fig.20 the relative between adc and offset voltage
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 44 12/14/2004 (v1.4) xii. timing diagrams fig.19 ac timing ins
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 45 12/14/2004 (v1.4) appendix i: describe of em78p5830d/ad (only list the difference between mask and otp) the em78p5830d is an 8-bit risc type microprocessor with low power, high speed cmos technology. there are 16kx13 bits electrical one time prog rammable read only memory (otp-rom) w ithin it. it provides security bits and some one time programmable option bits to protect the otp memory code from any external access as well as to meet user?s options. this integrated single chip has an on_chip watchdog timer (wdt), program otp-rom, data ram, programmable real time clock/counter, internal interrupt, power down mode, built-in three-wire spi, dual pwm(pulse width modulation), 8-channel 10-bit a/d converter and tri-state i/o. feature cpu ?e operating voltage : 2.2v~5.5v at main clk less then 3.58mhz. main clk(hz) under 3.58m 7.16m 10.74m 14.4m operating voltage(min) 2.2 2.5 3 3.6 ?e 16k x 13 on chip program memory. ?e 0.5k x 8 on chip data ram ?e up to 31 bi-directional tri-state i/o ports ?e 16 level stack for subroutine nesting ?e 8-bit real time clock/counter (tcc) ?e two 8-bit counters : counter1 and counter2 ?e on-chip watchdog timer (wdt) ?e 99.9 h single instruction cycle commands ?e four modes (main clock can be programmed from 447.829k to 14.3mhz generated by internal pll) mode cpu status main clock 32.768khz clock status sleep mode turn off turn off turn off green mode turn on turn off turn on normal mode turn on turn on turn on ?e input port interrupt function ?e 12 interrupt source, 4 external, 8 internal ?e dual clocks operation (internal pll main clock , external 32.768khz) spi ?e serial peripheral interface (spi) : a kind of serial i/o interface ?e interrupt flag available for the read buffer full, ?e programmable baud rates of communication ?e three-wire synchronous communication. (shared with io) pwm ?e dual pwm (pulse width modulation) with 10-bit resolution ?e programmable period (or baud rate) ?e programmable duty cycle adc ?e operating : 2.5v ?? 5.5v ?e 6-channel 10-bit successive approximation a/d converter ?e internal (vdd) or external reference por ?e 2.0v power-on voltage detector reset lcd ?e common driver pins : 4 ?e segment driver pins : 13 ?e 1/3 bias ?e 1/4 duty, 1/2 duty
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 46 12/14/2004 (v1.4) ?e 16 level lcd contrast control by software one time programmable rom burner pin otp pin name mask rom pin name p.s. vdd avdd vpp /reset dinck p65 aclk p64 pgmb p63 oeb p62 data p73 gnd avss em78p5830d code option register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pho versel adis mer /pot0 bit 0 (/pot0): program rom protect option. if set 1 to the bit, program memory can be access; else if clear this bit , program memory can not be access. bit 3(mer) : memory error recover function 0 ? disable memory error recover function 1 ? enable memory error recovery function if user enable memory error recovery function, mcu will improve effect from environment noise . bit 9(adis) : this bit must set to 1. bit 10 (versel): please clear this bit to 0. bit 11 (pho): please clear this bit to 0. dc electrical characteristic (ta = 25 c, avdd=vdd=5v 5%, vss=0v) parameter symbol condition min typ max unit output high voltage for port6, 8 voh2 ioh = -10ma 2.4 v output high voltage for port7, 9 voh3 ioh = -20ma 2.4 v output low voltage for port6, 8 vol2 ioh = 10ma 0.4 v output low voltage for port7, 9 vol3 ioh = 20ma 0.4 v appendix ii: notice about em785830ad developing tool. (ice5830) during developing program on ice5830, please fix these 3 bit (rd page1 bit4 ~ bit6) on initial and do not change them among program. rd page0 7 6 5 4 3 2 1 0 - versel pho adis - lcd_c1 lcd_c0 lcd_m r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 please clear versel and pho to 0 and set adis to 1 on initial.
em785830ad 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to be changed without notice. 47 12/14/2004 (v1.4) appendix iii: package spec of em785830ad, em78p5830d/ad

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